Output-based clock gating is a technique that is used to reduce the dynamic switching power of an integrated circuit. In particular, this technique analyzes an integrated circuit design to determine the conditions under which logic and clock switching frequency can be suppressed. These conditions are embodied in the form of clock enables (or logic equations), which are in turn synthesized into the original design to produce a clock-gated design.
One consequence of this technique is that the combinational equivalence between the original design and the clock-gated design is broken. That is, due to the addition of the clock enables in the clock-gated design, the combinational logic that generates the state values of the respective internal state elements will not be logically equivalent. It therefore becomes a challenge to verify that the clock-gated design is functionally identical to the original design.